Thermal monitoring mechanisms for chip multiprocessors
نویسندگان
چکیده
منابع مشابه
TSIC: Thermal Scheduling Simulator for Chip Multiprocessors
Increased power density, hot-spots, and temperature gradients are severe limiting factors for today’s state-of-the-art microprocessors. However, the flexibility offered by the multiple cores in future Chip Multiprocessors (CMPs) results in a great opportunity for controlling the chip thermal characteristics. When a process is to be assigned to a core, a thermal-aware scheduling policy may be in...
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Three-dimensional (3D) integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked high power density layers of 3D CMPs increase the importance and difficulty of thermal management. In this paper, we investigate the 3D CMP run-time thermal management problem and describe efficient management techniques. Th...
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Modern System-on-Chip (SOC) design shows a clear trend towards integration of multiple processor cores, the SOC System Section of the "International Technology Roadmap for Semiconductors" (http://public.itrs.net/) predicts that the number of processor cores will increase dramatically to match the processing demands of future applications. Providers like Intel, IBM, TI, Motorola, and Cradle have...
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ژورنال
عنوان ژورنال: ACM Transactions on Architecture and Code Optimization
سال: 2008
ISSN: 1544-3566,1544-3973
DOI: 10.1145/1400112.1400114